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H5TQ4G63CFR-RDC Dram Memory Chip 256MX16 CMOS PBGA96 Surface Mount High Efficiency

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Model Number :H5TQ4G63CFR-RDC

Certification :ORIGINAL PARTS

MOQ :1 package

Price :Negotiation

Payment Terms :T/T, PayPal, Western Union, Escrow and others

Supply Ability :10K per month

Delivery Time :3-5 work days

Packaging Details :tray package, 1600/box

ITEM NO. :H5TQ4G63CFR-RDC

Memory IC Type :DDR DRAM

Access Mode :MULTI BANK PAGE BURST

Package :R-PBGA-B96

Memory Width :16

Mounting :Surface Mount

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Dram Memory Chip H5TQ4G63CFR-RDC DDR DRAM, 256MX16, CMOS, PBGA96

The H5TQ4G63 is a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Features

VDD=VDDQ=1.5V +/- 0.075V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8 9 and 10
Programmable burst length 4/8 with both nibble sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of 0°C~ 95°C)
- 7.8 µs at 0°C ~ 85°C
- 3.9 µs at 85°C ~ 95°C Commercial Temperature( 0°C ~ 95°C) Industrial Temperature( -40°C ~ 95°C)
JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch

Technical Attributes

	Description	Value
	Address Bus Width	15 Bit
	Data Bus Width	16 Bit
	Density	4 Gb
	Lead Finish	Tin\|Silver\|Copper
	Maximum Clock Rate	934.57 MHz
	Maximum Operating Current	55 mA
	Maximum Random Access Time	20 ns
	Mounting	Surface Mount
	Number of Banks	8
	Number of Bits per Word	16 Bit
	Number of I/O Lines	16 Bit
	Operating Supply Voltage	1.5 V
	Operating Temperature	0 to 95 °C
	Organization	256M x 16
	Pin Count	96
	Product Dimensions	13 x 7.5 x 0.76
	Screening Level	Commercial
	Supplier Package	FBGA
	Type	DDR3 SDRAM

ECCN / UNSPSC

Product Tags:

Description	Value
ECCN:	EAR99
UNSPSC VERSION:	V15.1101
UNSPSC:	32101602