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DRAM Memory Chip DRAM Memory Chip H9HCNNN4KMMLHR 4Gb LPDDR4 BGA200 Memory Chip Storage
Features:
VDD1 = 1.8V (1.7V to 1.95V) · VDD2 and VDDCA = 1.1V (1.06V to 1.17V) · VDDQ = 0.6V (0.57V to 0.65V) · VSSQ terminated DQ signals (DQ, DQS_t, DQS_c, DMI) · Single data rate architecture for command and address; - all control and address latched at rising edge of the clock · Double data rate architecture for data Bus; - two data accesses per clock cycle · Differential clock inputs (CK_t, CK_c) · Bi-directional differential data strobe (DQS_t, DQS_c) - Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c) · DMI pin support for write data masking and DBIdc functionality · Programmable RL (Read Latency) and WL (Write Latency) · Burst length: 16 (default), 32 and On-the-fly - On the fly mode is enabled by MRS · Auto refresh and self refresh supported · All bank auto refresh and directed per bank auto refresh supported · Auto TCSR (Temperature Compensated Self Refresh) · PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask · Background ZQ Calibration
Part No. | Den.
| Org.
| Vol
| Speed
| Power
| PKG
| Product Status
|
---|---|---|---|---|---|---|---|
H9HCNNN4KMMLHR | 4Gb | x16 | 1.8V-1.1V-0.6V | L / M | Low Power | 200 | Mass production |
H9HCNNN4KUMLHR | 4Gb | x16 | 1.8V-1.1V-1.1V | L / M | Low Power | 200 | Mass production |
H9HCNNN8KUMLHR | 8Gb | x16 | 1.8V-1.1V-1.1V | L / M | Low Power | 200 | Mass production |
H9HCNNNBKMMLHR | 16Gb | x16 | 1.8V-1.1V-0.6V | M / E | Low Power | 200 | Mass production |
H9HCNNNBKUMLHR | 16Gb | x16 | 1.8V-1.1V-1.1V | M / E | Low Power | 200 | Mass production |
H9HCNNNBPUMLHR | 16Gb | x16 | 1.8V-1.1V-1.1V | L / M | Low Power | 200 | Mass production |
H9HCNNNCPMMLHR | 32Gb | x16 | 1.8V-1.1V-0.6V | M / E | Low Power | 200 | Mass production |
H9HCNNNCPUMLHR | 32Gb | x16 | 1.8V-1.1V-1.1V | M / E | Low Power | 200 | Mass production |
Part Number | Speed |
---|---|
L | 3200Mbps |
M | 3733Mbps |